View CP2110-F01-GM_7650006.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. 1.1 3/11 copyright ? 2011 by silicon laboratories cp2110 cp2110 s ingle -c hip hid usb to uart b ridge single-chip hid usb to uart data transfer ?? integrated usb transceiver ; no external resistors required ?? integrated clock; no external crystal required ?? integrated 343-byte one-time programmable rom for storing customizable product information ?? on-chip power-on reset circuit ?? on-chip voltage regulator: 3.45 v output usb peripheral function controller ?? usb specification 2.0 compliant; full-speed (12 mbps) ?? usb suspend states supported via suspend pins hid interface ?? standard usb class device requires no custom driver ?? windows 7, vista, xp, server 2003, 2000 ?? win ce 6.0, 5.0, and 4.2 ?? mac os-x ?? linux ?? open access to inte rface specification windows and mac hid-to-uart libraries ?? apis for quick application development ?? supports windows 7, vista, xp, server 2003, 2000 ?? supports mac os x supply voltage ?? self-powered: 3.0 to 3.6 v ?? usb bus powered: 4.0 to 5.25 v ?? i/o voltage: 1.8 v to v dd uart interface features ?? flow control options: - hardware (cts / rts) - no flow control ?? data formats supported: - data bits: 5, 6, 7, and 8 - stop bits: 1, 1.5, and 2 - parity: odd, even, mark, space, no parity ?? baud rates: 300 bps to 1 mbps ?? 480 byte receive and transmit buffers ?? rs-485 mode with bus transceiver control ?? line break transmission gpio interface features ?? 10 gpio pins with configurable options ?? usable as inputs, open-drain or push-pull outputs ?? configurable clock output for external devices - 24 mhz to 47 khz ?? rs-485 bus transceiver control ?? toggle led upon transmission ?? toggle led upon reception ordering part numbers ?? CP2110-F01-GM (qfn24, 4 x 4 mm, pb-free) ?? cp2110-f02-gm1 (qfn28, 5 x 5 mm, pb-free) - qfn28 is pin-compatible with the cp2102-gm. temperature range: ?40 to +85 c figure 1. example system diagram connect to vbus or external supply vbus d+ d- gnd usb connector logic level supply (1.8v to vdd) uart and flow control gpio signals cp2110 data fifos 48 mhz oscillator 480 b rx 480 b tx uart controller usb interface peripheral function controller full-speed 12 mbps transceiver 343 byte prom (product customization) voltage regulator baud rate generator regin vdd gnd vio vbus d+ d- i/o power and logic levels rst gpio and suspend controller tx rx gpio.1_rts gpio.2_cts suspend signals gpio.0_clk gpio.3_rs485 gpio.4_txt gpio.5_rxt gpio.6 gpio.7 gpio.8 gpio.9 suspend suspend vpp
cp2110 2 rev. 1.1
cp2110 rev. 1.1 3 t able of c ontents section page 1. system overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3. pinout and package defini tions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4. qfn-24 package specificati ons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5. qfn-28 package specificati ons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6. usb function controller and transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7. asynchronous seri al data bus (uart) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8. gpio pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.1. gpio.0?clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.2. gpio.1-2?hardware flow contro l (rts and cts) . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.3. gpio.3?rs-485 transceive r bus control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.4. gpio.4-5?transmit and re ceive toggle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9. one-time programmable rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 10. voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 11. cp2110 interface specification a nd windows interface dll . . . . . . . . . . . . . . . . . . . . 24 12. relevant application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
cp2110 4 rev. 1.1 1. system overview the cp2110 is a highly-integrated hid usb-to-uart bri dge controller providing a simple solution for updating rs-232 designs to usb using a minimum of components and pcb space. the cp2110 includes a usb 2.0 full- speed function controller, usb transc eiver, oscillator, one-time programmabl e rom, and an asynchronous serial data bus (uart) in compact 4 x 4 mm qfn24 and 5 x 5 mm qfn28 packages (sometimes called ?mlf? or ?mlp?). the on-chip, one-time programmable rom provides the op tion to customize the usb vendor id, product id, manufacturer product string, product description string, power descriptor, device release number, device serial number, and gpio configuration as desired for oem applications. the cp2110 uses the standard usb hid device class which is natively supported by most operating systems. a custom driver does not need to be installed for this device. windows applications communicate with the cp2110 through a windows dll which is prov ided by silicon labs. the interface sp ecification for the cp2110 is also available to enable development of an api fo r any operating system that supports hid. note: the cp2110 devices will not enumerate as a standard hid mouse or keyboard. the cp2110 uart interface implements all rs-232 sign als, including control and hardware handshaking, so existing system firmware does not ne ed to be modified. the uart capabilit ies of the cp2110 include baud rate support from 300 to 1 mbps, hardware flow control, support for 5-8 data bits, 5 types of parity and rs-485 support. the device also features a total of 10 gpio signals that are user-defined for status and control information. six of the gpio signals support alternate features including hard ware flow control (rts and cts), a configurable clock output (24 mhz to 47 khz), rs-485 transceiver control, and tx and rx led toggle. on the -gm packages, support for i/o interface voltages down to 1.8 v is provided via a v io pin. on the -gm1 packages, the v io pin is internally tied to vdd. an evaluation kit for the cp2110 (part number: cp2110 ek) is available. it includes a cp2110-based usb-to- uart/rs-232 evaluation board, windows dll and test application, usb and rs-232 cables, and full documentation. see www.silabs.com for the latest application notes and product support information for the cp2110. contact a silicon labs sales representatives or go to www.silabs.com to order the cp2110 evaluation kit.
cp2110 rev. 1.1 5 2. electrical characteristics table 1. absolute maximum ratings parameter conditions min typ max units ambient temperature under bias ?55 ? 125 c storage temperature ?65 ? 150 c voltage on rst , gpio or uart pins with respect to gnd v io > 2.2 v v io < 2.2 v ?0.3 ?0.3 ? ? 5.8 v io + 3.6 v voltage on v dd or v io with respect to gnd ?0.3 ? 4.2 v maximum total current through v dd , v io , and gnd ? ? 500 ma maximum output current sunk by rst or any i/o pin ? ? 100 ma note: stresses above those listed may cause permanent damage to t he device. this is a stress rating only, and functional operation of the devices at or exceeding the conditions in th e operation listings of this sp ecification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 2. global dc electrical characteristics v dd = 3.0 to 3.6 v, ?40 to +85 c unless otherwise specified. parameter conditions min typ max units digital supply voltage (v dd ) 3.0 ? 3.6 v digital port i/o supply voltage (v io ) -gm packages only v dd = v io on -gm1 1.8 ? v dd v supply current 1 normal operation; v reg enabled ?11.312.5ma supply current 1 suspended; v reg enabled ?120220a supply current - usb pull-up 2 ?200228a specified operating temperature range ?40 ? +85 c notes: 1. if the device is connected to the usb bus, the usb pull-up current should be added to the supply current to calculate total required current. 2. the usb pull-up supply current values are calc ulated values based on usb specifications.
cp2110 6 rev. 1.1 table 3. uart and suspend i/o dc electrical characteristics v io = 1.8 to 3.6 v, ?40 to +85 c unless otherwise specified. parameters conditions min typ max units output high voltage (v oh )i oh =?10a i oh =?3ma i oh =?10ma v io ?0.1 v io ?0.2 ? ? ? v io ?0.4 ? ? ? v output low voltage (v ol )i ol =10a i ol =8.5ma i ol =25ma ? ? ? ? ? 0.6 0.1 0.4 ? v input high voltage (v ih ) 0.7 x v io ??v input low voltage (v il )??0.6v input leakage current weak pull-up off weak pull-up on, v io = 0 v ? ? ? 25 1 50 a maximum input voltage open drain, logic high (1) ? ? 5.8 v table 4. reset electrical characteristics ?40 to +85 c unless otherwise specified. parameter conditions min typ max units rst input high voltage 0.75 x v io ??v rst input low voltage ? ? 0.6 v minimum rst low time to generate a system reset 15 ? ? s
cp2110 rev. 1.1 7 table 5. voltage regulator electrical specifications ?40 to +85 c unless otherwise specified. parameter conditions min typ max units input voltage range 3.0 ? 5.25 v output voltage output current = 1 to 100 ma* 3.3 3.45 3.6 v vbus detection input threshold 2.5 ? ? v bias current ? ? 120 a *note: the maximum regulator supply current is 100 ma. this includes the supply current of the cp2110 . table 6. gpio output specifications ?40 to +85 c unless otherwise specified. parameter conditions min typ max units gpio.0 clock output output x 0.985 output 1 output x 1.015 hz rs-485 active time after stop bit ? 1 ? bit time 2 tx toggle rate ? 10 ? hz rx toggle rate ? 10 ? hz 1. the output frequency is configurable from 24 mhz to 47 khz. 2. bit-time is calculated as 1/baud rate.
cp2110 8 rev. 1.1 3. pinout and p ackage definitions table 7. cp2110 pin definitions name -gm qfn24 -gm1 qfn28 type description v dd 66power in power out power supply voltage input. voltage regulator output. see section 10. v io 5 power in i/o supply voltage input. internally connected to v dd on -gm1 packages. gnd 2 3 ground. must be tied to ground. rst 9 9 d i/o device reset. op en-drain output of internal por or v dd monitor. an external source can initiate a system reset by driving this pin low for the time specified in table 4. regin 7 7 power in 5 v regulator input. this pin is the input to the on-chip voltage regulator. vbus 8 8 d in vbus sense input. this pin should be connected to the vbus signal of a usb network. v pp 16* 18* special connect 4.7 ? f capacitor between this pin and ground to support rom programming via the usb interface. d+ 3 4 d i/o usb d+ d? 4 5 d i/o usb d? tx 21 26 d out asynchronous data output (uart transmit) for the uart interface. rx 20 25 d in asynchronous data input (uart receive) for the uart interface. gpio.0 clk 1* 2* d i/o d out in gpio mode, this pin is a us er-configurable input or output. in clk mode, this pin outputs a co nfigurable frequency clock signal. gpio.1 rts 24* 24* d i/o d out in gpio mode, this pin is a us er-configurable input or output. in hardware flow control mode, this pin is the ready to send control output (active low) for the uart interface. gpio.2 cts 23* 23* d i/o d in in gpio mode, this pin is a us er-configurable input or output. in hardware flow control mode, this pi n is the clear to send control input (active low) for th e uart interface. gpio.3 rs485 22* 1* d i/o d out in gpio mode, this pin is a us er-configurable input or output. in rs-485 mode, this pin is the transmit active pin for the rs-485 transceiver. *note: pins can be left unconnected when not used.
cp2110 rev. 1.1 9 gpio.4 txt 19* 28* d i/o d out in gpio mode, this pin is a us er-configurable input or output. in txt mode, this pin is the transmi t toggle pin and toggles to indicate uart transmission. the pin is logic high when a transmission is not in progress. gpio.5 rxt 18* 27* d i/o d out in gpio mode, this pin is a user-c onfigurable input or output for the standard comm interface. in rxt mode, this pin is the receive toggle pin. the pin is logic high when the uart is not receiving data. gpio.6 15* 19* d i/o this pin is a us er-configurable input or output. gpio.7 14* 17* d i/o this pin is a us er-configurable input or output. gpio.8 13* 16* d i/o this pin is a us er-configurable input or output. gpio.9 12* 10* d i/o this pin is a us er-configurable input or output. suspend 11* 12* d out this pin is logic high wh en the cp2110 is in the usb suspend state. suspend 17* 11* d out this pin is logic low when t he cp2110 is in the usb suspend state. n/c 10* 13, 14, 15, 20, 21, 22* no connect. this pin should be left unconnected or tied to v io . table 7. cp2110 pin definitions (continued) name -gm qfn24 -gm1 qfn28 type description *note: pins can be left unconnected when not used.
cp2110 10 rev. 1.1 figure 2. qfn-24 pinout diagram (top view) 24 23 22 21 20 19 1 2 3 4 5 6 7 8 9 10 11 12 18 17 16 15 14 13 gnd (optional) cp2110-gm top view gpio.4_txt rx tx gpio.3_rs485 gpio.2_cts gpio.1_rts gpio.0_clk gnd d+ n/c suspend gpio.9 gpio.5_rxt gpio.8 gpio.7 gpio.6 vpp suspend vdd vio d- rst vbus regin
cp2110 rev. 1.1 11 figure 3. qfn-28 pinout diagram (top view) 3 4 5 1 2 10 11 8 9 19 18 17 21 20 26 27 28 24 25 gpio.0_clk gnd d+ d? rst gpio.9 suspend suspend gpio.7 vpp gpio.6 n.c. n.c. rxd gpio.5_rxt gpio.4_txt txd cp2110-gm1 top view gnd (optional) 7 6 12 13 14 vdd regin n.c. n.c. 16 15 n.c gpio.8 22 23 n.c. gpio.2_cts gpio.1_rts vbus gpio.3_rs485
cp2110 12 rev. 1.1 4. qfn-24 package specifications figure 4. qfn-24 package drawing table 8. qfn-24 package dimensions dimension min typ max dimension min typ max a 0.70 0.75 0.80 l 0.30 0.40 0.50 a1 0.00 0.02 0.05 l1 0.00 ? 0.15 b 0.18 0.25 0.30 aaa ? ? 0.15 d 4.00 bsc. bbb ? ? 0.10 d2 2.55 2.70 2.80 ddd ? ? 0.05 e 0.50 bsc. eee ? ? 0.08 e 4.00 bsc. z ? 0.24 ? e2 2.55 2.70 2.80 y ? 0.18 ? notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jedec solid state outline mo-220, variation wggd except for custom features d2, e2, z, y, and l wh ich are toleranced per supplier designation. 4. recommended card reflow profile is per the jede c/ipc j-std-020 specific ation for small body components.
cp2110 rev. 1.1 13 figure 5. qfn-24 recommended pcb land pattern table 9. qfn-24 pcb land pattern dimensions dimension min max dimension min max c1 3.90 4.00 x2 2.70 2.80 c2 3.90 4.00 y1 0.65 0.75 e 0.50 bsc y2 2.70 2.80 x1 0.20 0.30 notes: general 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. this land pattern design is based on the ipc-7351 guidelines. solder mask design 3. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 ? m minimum, all the way around the pad. stencil design 4. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 5. the stencil thickness should be 0.125 mm (5 mils). 6. the ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 7. a 2 x 2 array of 1.10 x 1.10 mm openings on a 1.30 mm pitch should be used for the center pad. card assembly 8. a no-clean, type-3 solder paste is recommended. 9. the recommended card reflow profile is per t he jedec/ipc j-std-020 specification for small body components.
cp2110 14 rev. 1.1 5. qfn-28 package specifications figure 6. qfn-28 package drawing table 10. qfn-28 package dimensions dimension min typ max dimension min typ max a 0.80 0.90 1.00 l 0.35 0.55 0.65 a1 0.00 0.02 0.05 l1 0.00 ? 0.15 a3 0.25 ref aaa 0.15 b 0.18 0.23 0.30 bbb 0.10 d 5.00 bsc. ddd 0.05 d2 2.90 3.15 3.35 eee 0.08 e 0.50 bsc. z 0.44 e 5.00 bsc. y 0.18 e2 2.90 3.15 3.35 notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jedec solid state out line mo-220, variation vhhd except for custom features d2, e2, l, z, and y which are toleranced per supplier designation. 4. recommended card reflow profile is per the jede c/ipc j-std-020 specific ation for small body components.
cp2110 rev. 1.1 15 figure 7. qfn-28 recommended pcb land pattern table 11. qfn-28 pcb land pattern dimensions dimension min max dimension min max c1 4.80 x2 3.20 3.30 c2 4.80 y1 0.85 0.95 e 0.50 y2 3.20 3.30 x1 0.20 0.30 notes: general 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. this land pattern design is based on the ipc-7351 guidelines. solder mask design 3. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 ? m minimum, all the way around the pad. stencil design 4. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 5. the stencil thickness should be 0.125 mm (5 mils). 6. the ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 7. a 3 x 3 array of 0.90 mm openings on a 1.1 mm pitc h should be used for the center pad to assure the proper paste volume (67% paste coverage). card assembly 8. a no-clean, type-3 solder paste is recommended. 9. the recommended card reflow profile is per t he jedec/ipc j-std-020 specification for small body components.
cp2110 16 rev. 1.1 6. usb function controller and transceiver the universal serial bu s (usb) function controller in the cp2110 is a usb 2.0-compliant, full-speed device with integrated transceiver and on-chip matching and pullup re sistors. the usb function controller manages all data transfers between the usb and the uarts as well as command requests generated by the usb host controller and commands for controlling the function of the uarts and gpio pins. the usb suspend and resume modes are supported for power management of both the cp2110 device as well as external circuitry. the cp2110 enters suspend mode when suspend signaling is detected on the bus. upon entering suspend mode, the suspend signals are asserted. the suspend signals are also asserted after a cp2110 reset until device configurati on during usb enumeration is complete. su spend is logic high when the device is in the suspend state, and logic low when th e device is in normal mode. the suspend pin has the opposite logic value of the suspend pin. the cp2110 exits suspend mode when any of the following occur: resume signaling is detected or generated, a usb reset signal is detected, or a device reset occurs. suspend and suspend are weakly pulled to vio in a high impedance state during a cp2110 reset. if this behavior is undesirable, a strong pulldown (10 k ? ) can be used to ensure suspend remains low during reset. the logic level and output mode (push-pull or open-drain) of various pins during usb suspend is configurable in the prom. see section 9 for more information.
cp2110 rev. 1.1 17 7. asynchronous serial data bus (uart) interface the uart interface consists of the tx (transmit) and rx (receive) data si gnals as well as the optional rts and cts flow control signals. the uart is programmable to su pport a variety of data formats and baud rates. the data format and baud rate are set during device configurati on on the pc. the data formats and baud rates available to each interface are listed in table 12. the baud rate generator for the uart interface is very flex ible and allows the user to request any baud rate in the range from 300 bps to 1 mbps. if the baud rate cannot be directly generated fr om the internal 24 mhz oscillator, the device will choose the closest possible option. the actual baud rate is dictated by equation 1 and equation 2. equation 1. clock divider calculation equation 2. baud rate calculation most baud rates can be generated with an error of less than 1.0%. a general rule of thumb for the majority of uart applications is to limit the baud rate error on both the transmitter and the receiver to no more than 2%. the clock divider value obtained in equation 1 is rounded to the nearest integer, which may produce an error source. another error source will be the 24 mhz oscill ator, which is accurate to 0.25%. knowing the actual and requested baud rates, the total baud rate error can be found using equation 3. equation 3. baud rate error calculation the uart also supports the transmission of a line break. the length of time for a line break is programmable from 1 to 125 ms, or it can be set to transmit indefinitely until a stop command is sent from the application. table 12. data formats and baud rates data bits 5, 6, 7, and 8 stop bits 1, 1.5 1 , and 2 parity type none, even, odd, mark, space baud rate 300 bps to 1 mbps 2 notes: 1. 1.5 stop bits only available when using 5 data bits. 2. baud rates above 500,000 baud not supported with 5 or 6 data bits. clock divider 24 mhz 2 prescale requested baud rate ? ? ---------------------------------------------------------------------------------------------------- = prescale 4 if requested baud rate 300 bps ? = prescale 1 if requested baud rate 300 bps ? = actual baud rate 24 mhz 2 prescale clock divider ? ? ---------------------------------------------------------------------------- - = prescale 4 if requested baud rate 300 bps ? = prescale 1 if requested baud rate 300 bps ? = baud rate error (%) 100 1 actual baud rate requested baud rate ---------------------------------------------------------- - ? ?? ?? ? 0.25% ? =
cp2110 18 rev. 1.1 8. gpio pins the cp2110 supports 10 user-configurable gpio pins. each of these gpio pins are usable as inputs, open-drain outputs, or push-pull outputs. six of these gpio pins also have alternate functions which are listed in table 13. more information regarding the configuration and us age of these pins is av ailable in ?an144: cp21xx customization guide? available on the silicon labs website. the default configuration for all of the gpio pins is provided in table 14. the configuration of the pins is one-time programmable for each device. see section 9 for more information about programming the gpio pin functionality. the difference between an open-drain output and a push-pu ll output is when the gpio output is driven to logic high. a logic high, open-drain output pulls the pin to the vi o rail through an internal, pull-up resistor. a logic high, push-pull output directly connects the pin to the vio voltage. open-dra in outputs are typically used when interfacing to logic at a higher voltage than the vio pin. these pins can be safely pulled to the higher, external voltage through an external pull-up resistor. the maximum external pull-up voltage is 5 v. the speed of reading and writing the gp io pins is subject to the timing of the usb bus. gpio pins configured as inputs or outputs are not recomm ended for real-time signalling. table 13. gpio pin alternate functions gpio pin alternate function gpio.0 clk output gpio.1 rts gpio.2 cts gpio.3 rs-485 transceiver control gpio.4 tx toggle gpio.5 rx toggle table 14. gpio pin default configuration gpio pin default function gpio pin default function gpio.0 gpio input gpio.5 rx toggle gpio.1 rts gpio.6 gpio input gpio.2 cts gpio.7 gpio input gpio.3 rs-485 transceiver control gpio.8 gpio push-pull output gpio.4 tx toggle gpio.9 gpio push-pull output
cp2110 rev. 1.1 19 8.1. gpio.0?clock output gpio.0 is configurable to output a configurable cmos cl ock output. the clock output appears at the pin at the same time the device completes enumeration and exits u sb suspend mode. the clock output is removed from the pin when the device enters usb suspend mode. the output frequency is configurable through the use of a divider and the accuracy is specified in table 6. when the divider is set to 0, the output frequency is 24 mhz. for divider values between 1 and 255, the output fr equency is determined by the formula: equation 4. gpio.0 clock output frequency this divider is independent from the divider used to set uart baud rate. 8.2. gpio.1-2?hardware fl ow control (rts and cts) by default, gpio.1 and gpio.2 are configured to operate as the hardware flow control pins rts and cts. in addition to the gpio prom configuration, the device must be configured to use hardware flow control to use these pins. rts, or ready to send, is an active-low output from th e cp2110 and indicates to the external uart device that the cp2110?s uart rx fifo has not reached the watermark level of 450 bytes and is ready to accept more data. when the amount of data in the rx fifo reaches the wa termark, the cp2110 pulls rt s high to indicate to the external uart device to stop sending data. cts, or clear to send, is an active-low input to the cp21 10 and is used by the external uart device to indicate to the cp2110 when the external uart de vice?s rx fifo is getting full. t he cp2110 will not send more than two bytes of data once cts is pulled high. figure 8. hardware flow control typical connection diagram gpio.0 clock frequency 24 mhz 2divider ? ----------------------------- - = cp2110 rs232 system tx rx tx rx rts cts gpio.1 ? rts gpio.2 ? cts
cp2110 20 rev. 1.1 8.3. gpio.3?rs-485 tr ansceiver bus control gpio.3 is configurable as an rs-485 bus transceiv er control pin that is connected to the de and re inputs of the transceiver. when configured for rs-485 mode, the pin is as serted during uart data transmission as well as line break transmission. the rs-485 mode of gpio.3 is active-high by default, but is also configurable for active-low mode. figure 9. rs-485 transceiver typical connection diagram 8.4. gpio.4-5?trans mit and receive toggle gpio.4 and gpio.5 are configurable as transmit toggle and receive toggle pins. these pins are logic high when a device is not transmitting or receiving data, and they toggle at a fixed rate as specified in table 6 when data transfer is in progress. typically, these pins are connected to two leds to indicate data transfer. figure 10. transmit and receive toggle typical connection diagram more information regarding the configuration and usage of th ese pins can be found in section 9 as well as ?an144: cp21xx customization guide? availa ble on the silicon labs web site. rs485 transceiver r d de re cp2110 tx rx gpio.3 ? rs485 cp2110 gpio.4 ? tx toggle gpio.5 ? rx toggle vio
cp2110 rev. 1.1 21 9. one-time programmable rom the cp2110 includes an internal, one-time programmable rom that may be used to customize the usb vendor id (vid), product id (pid), manufactur er string, product description string , power descriptor, device release number, device serial number, gpio configuration, susp end pins and modes as desired for oem applications. if the programmable rom has not been customized, the default configuration data shown in table 15 and table 16 is used. while customization of the usb confi guration data is optional, customizing the vid/pid combi nation is strongly recommended. a unique vid/pid will pr event the device from being reco gnized by any other manufacturer?s software application. a vendor id c an be obtained from www.usb.org or silicon labs can provide a free pid for the oem product that can be used with t he silicon labs vid. all cp2110 devi ces are pre-progra mmed with a unique serial number. it is important to have a unique serial if it is possible for multip le cp2110-based devices to be connected to the same pc. application note ?an433: cp2110 hid interface specification? includes mo re information about the programmable values and their valid options. note that certain items in the prom are programmed as a group and programming one of the items in the group prevents further prog ramming of any of the other items in the group. the configuration data rom is progra mmable by silicon labs prior to ship ment with the desired configuration information. it can also be programmed in-system over the usb interface by adding a capacitor to the pcb. if the configuration rom is to be programmed in-system, a 4. 7 f capacitor must be added between the vpp pin and ground. no other circuitry shou ld be connected to vpp during a programming operation, and v dd must remain at 3.3 v or higher to successfully write to the configuration rom. table 15. default usb configuration data name value vendor id 10c4h product id ea80h power descriptor (attributes) 80h (bus-powered) power descriptor (max. power) 32h (100 ma) release number 0100h (release version 01.00) manufacturer string ?silic on laboratories? (62 asc ii characters maximum) product description string ?cp2110 hid usb-to -uart bridge? (62 ascii characters maximum) serial string unique 8 character ascii string (30 ascii characters maximum) table 16. default gpio, uart, and suspend configuration data name value name value gpio.0 gpio input gpio.9 gpio push-pull output gpio.1 rts flush_buffers flush tx and rx fifo on open gpio.2 cts tx mode push-pull gpio.3 rs-485 transceiver co ntrol suspend mode push-pull gpio.4 tx toggle suspend mode push-pull gpio.5 rx toggle suspend latch 0x0000 gpio.6 gpio input suspend mode 0x0000 gpio.7 gpio input rs-485 level active high gpio.8 gpio push-pull output clock divider divide by 1 (24 mhz)
cp2110 22 rev. 1.1 10. voltage regulator the cp2110 includes an on-chip 5 to 3.45 v voltage regulato r. this allows the cp2110 to be configured as either a usb bus-powered device or a usb self-powered device. a typical connection diagram of the device in a bus- powered application using the regulator is shown in figure 11. when enabled, the voltage regulator output appears on the v dd pin and can be used to power external devices. see table 5 for the voltage regulator electrical characteristics. if the regulator is used to provide v dd in a self-powered applicati on, use the same connections from figure 11, but connect regin to an on-board 5 v supply, and disconnect it from the vbus pin. figure 11. typical bus-powered connection diagram note 3 note 2 vbus d+ d- gnd usb connector suspend signals standard uart and gpio signals cp2110 gpio.0_clk gpio.1_rts gpio.2_cts gpio.3_rs485 tx rx vpp suspend suspend gpio.4_txt gpio.5_rxt gpio.8 gpio.9 gpio.6 gpio.7 vbus d+ d- rst vio 4.7 k note 4 note 1 : vio can be connected directly to vdd or to a supply as low as 1.8 v to set the i/o interface voltage. vio is internally connected to vdd on -gm1 packages. note 2 : avalanche transient voltage suppression diodes compatible with full-speed usb should be added at the connector for esd protection. use littelfuse p/n sp0503baht or equivalent. note 3 : an external pull-up is not required, but can be added for noise immunity. note 4 : if programming the configuration rom via usb, add a 4.7 ? f capacitor between vpp and ground. during a progra mming operation, do not co nnect the vpp pin to other circuitry, and ensure that vdd is at least 3.3 v. 4.7 ? f note 1 regin vdd gnd vio 1 ? f 1-5 ? f 0.1 ? f 3.45 v power
cp2110 rev. 1.1 23 alternatively, if 3.0 to 3.6 v power is supplied to the v dd pin, the cp2110 can function as a usb self-powered device with the voltage regulator bypassed. for this configuration, tie the regin input to v dd to bypass the voltage regulator. a typical connection diagram showing the dev ice in a self-powered app lication with the regulator bypassed is shown in figure 12. the usb max power and power attributes descriptor must match the device power usage and configuration. see application note ?an144: cp21xx customization guide? for information on how to customize usb descriptors for the cp2110. figure 12. typical self-powered connection diagram (regulator bypass) note 1 note 3 note 2 vbus d+ d- gnd usb connector suspend signals standard uart and gpio signals cp2110 gpio.0_clk gpio.1_rts gpio.2_cts gpio.3_rs485 tx rx vpp suspend suspend gpio.4_txt gpio.5_rxt gpio.8 gpio.9 gpio.6 gpio.7 vdd regin gnd vio vbus d+ d- rst 0.1 ? f 1-5 ? f vio 4.7 k note 4 note 1 : vio can be connected directly to vdd or to a supply as low as 1.8 v to set the i/o interface voltage. vio is internally connected to vdd on -gm1 packages. note 2 : avalanche transient voltage suppression diodes compatible with full-speed usb should be added at the connector for esd protection. use littelfuse p/n sp0503baht or equivalent. note 3 : an external pull-up is not required, but can be added for noise immunity. note 4 : if programming the configuration rom via usb, add a 4.7 ? f capacitor between vpp and ground. during a programming operation, do not connect the vpp pin to other circuitry, and ensure that vdd is at least 3.3 v. 4.7 ? f 3.3 v power
cp2110 24 rev. 1.1 11. cp2110 interface specificati on and windows interface dll the cp2110 is a usb human interface device (hid), and as most operating systems include native hid drivers, custom drivers do not need to be installed. the cp2110 does not fit one of the standard hid device types, such as a keyboard or mouse, and so any cp2110 pc applicat ion needs to use the cp21 10?s hid specification to communicate with the device. the low-level hid specificat ion for the cp2110 is provided in ?an434: cp2110 hid interface specification.? this document describes all of the basic functions for opening, reading from, writing to, and closing the device as well as the rom programming functions. a windows dll that encapsulates the cp2110 hid interfac e and also adds higher level features such as read/ write time-outs is provided by silic on labs. this dll is the recommended in terface for the cp2110. the windows dll is documented in cp2110 windows dll specification . both of these documents and the dll are available in the cp2110ek cd as well as online at http://www.silabs.com/. 12. relevant ap plication notes the following application notes are app licable to the cp2110. the latest ve rsions of these application notes and their accompanying software are available at http://www.silabs.com/products/mcu /pages/applicationnotes.aspx . ? an144: cp21xx device customization guide. this application note describes how to use the an144 software cp2110setids to configure the usb parameters on the cp2110 devices. ? an434: cp2110 hid interface specification. this application note describes how to interface to the cp2110 using the low-level, hid interface. ? an433: cp2110 hid to uart api specification. this application note descri bes how to inte rface to the cp2110 using the windows interface dll and the mac os x dylib.
cp2110 rev. 1.1 25 d ocument c hange l ist revision 1.0 to revision 1.1 ? added support for new cp2110-gm1 package throughout document.
cp2110 26 rev. 1.1 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders the information in this document is believed to be accurate in a ll respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and om issions, and disclaims respons ibility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratories assumes no re sponsibility for the functioning of und escribed fea- tures or parameters. silicon laboratories reserves the right to make changes without further notice. silicon laboratories makes no warranty, representation or guarantee regarding the suitability of its pr oducts for any particular purpose, nor does silicon laboratories assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, in cluding without limitation consequential or incidental damages. silicon laboratories products are not designed, intended, or authorized for use in applica tions intend- ed to support or sustain life, or for any other application in which the failure of the silicon laboratories product could crea te a situation where personal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unaut horized application, buyer sha ll indemnify and hold silicon laboratories harmless against all claims and damages.

▲Up To Search▲

Price & Availability of CP2110-F01-GM

	To Download CP2110-F01-GM Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .